For reference and future similar investigations :

     The power supply was tested using a DC block (here up to 50V).

     The ground was tested with the power supply disconnected.

Marc, Michael, Yuhang

We checked the resistor and noise spectrum of several points on DDS board.

Brief introduction of DDS board configuration: Power supply (24V) > voltage regulator (1.8V goes to generate signal, 3.3V goes to power up chip/USB) > 1.8V > AVDD point> DDS process > filter-in point > 200MHz low pass filter > filter-out point > to be used

Figure 1~3 show resistors from ground to:

AVDD: 0.83kOhm

filter-in: very high (seems to be not connected)

filter-out: 2.7Ohm

Figure 4 shows the noise spectrum of those points and power supply.

We could see that power supply is clean. But once DDS board is connected, almost every point inside DDS board show ~20kHz peaks.

Marc and Yuhang

To understand if ~20kHz noise is present as sidebands of RF signals, for DDS2, we checked RF signals coming from CH0 and CH1 with spectrum analyzer.

Figure 1 shows 78MHz signal coming out from CH1 on spectrum analyzer. For this singal, we could see:

1. It has noise shoulder, which is between 0~3kHz.

2. We don't see any noise peak around 20kHz.

Then we checked also CH0, which shows the same behavior.

Since we don't see 20kHz peak around RF signal, we tried to use CH0 to demodulate CH1 and we did't expect to see ~20kHz peak.  (Note that RF amplifier was used for CH0 in this measurement) Figure 2 shows the demodulated signal spectrum. Peaks around 20kHz show up clearly in this spectrum. This means that these peaks doesn't come from RF signals but they were just there (actually everywhere).

Marc and Yuhang

We checked again the connection from ground to power supply or signal output today. And we realize that we were not checking in a good way last week.

This time, we measured the resistor between ground and many other parts. We found the resistor is as high as from 0.3kOhm to 0.9kOhm. In this case, it means the ground is well isolated with those channels. So there should not be ground issue.

Participants : Marc, Yuhang

To test the effect of the amplifier we checked the spectrum of CH0 when disconnecting the amplifier :

    FIg1 shows the CH0 spectrum when the voltage supply of the amplifier is disconnected but amplifier is still connected to CH2.

     Fig2 shows the same with the ground also disconnected.

     Fig3 shows the CH0 without the amplifier at all.

In all these configurations the peak around 20kHz is present : The 20kHz peak does not arise from the amplifier

We used the spectrum analyzer of the elec shop to check if the 20kHz peak is present in the voltage supply of this board.

     Fig4 shows in yellow CH0 and blue the 1.8V supply : same peak in both at 17.4 kHz

     Fig5 shows in yellow CH0 and blue before the regulator of the 1.8V supply : same as previous

     Fig6 shows in yellow CH0 and blue the 24V supply : same as previous

Finally, we found out that the ground may be connected to all voltage supply of this board as well as DDS output channels (see connection.mp4)

Participants : Marc, Yuhang

We locked the SHG and connect only DDS3 to its power supply. The peaks are still present on the SHG error signal.

We checked each output channel of this DDS3 with the spectrum analyzer :

     No peaks present from CH0 nor CH1 (Fig1).

     CH2 exhibits a peak at 21.957 kHz (Fig2) at exact same frequency as the peak on SHG error spectrum ! (note that the peak freauency changed with respect to yesterday measurement. Also we checked that it changes by few hundred Hz within ~10mn)

     As the CH2 output is connected to a splitter, we also checked the splitter second output which also exhibits a similar peak (Fig3).

    We disconnected all outputs from DDS3 but the peaks are still present on the SHG error signal (Fig4).

Remind that we added an amplifier to each channel of DDS3 which could mean that the problem does not arise from the amplifier itself. Only difference between these channels output is that CH0,1 and 3 have attenuators at their output but not CH2.

     We removed attenuator from CH0 and a peak at around 20 kHz appeared (fig5).

We then tested DDS2 (as it has only 1 amplifier).

SHG ERR signal exhibits peak at 17.4kHz (Fig6)

    CH1 (amplifier, no attenuator at its output) : only harmonic visible in Fig7

     DDCH0 ( no amplifier, no attenuator) : clear peaks in Fig8

The conclusion seems to be that the amplifier is not the culprit.

Participants : Marc, Yuhang

Here are the figures :

First no DDS board connected to the rack : all the peaks disappear.

Then, DDS board connected one by one we can see that each DDS is causing one of the peak around 20 kHz.

DDS1 -> 18 112 Hz

DDS2 -> 17 728 Hz

DDS3 -> 21 312 Hz

Marc and Yuhang

We used signal generator AFG3102 to modu/demodu SHG fields (instead of DDS1). At the same time, all DDS boards were taken out from rack. Then we locked SHG and checked error signal spectrum. We found 20kHz noise disappeared. Figure 1 (SHGNODDS.txt) shows error signal spectrum in this measurement.

After that we also checked the rack voltage, which may change due to large power consumption.

We measured error signals when there were DDS1 only (DDS1.txt), DDS2 only (DDS2.txt), DDS3 only (DDS3.txt) and clock removed (no clock.tx).

Marc, Michael, Yuhang

The issue of SHG error signal happened after installing amplifiers for DDS1 board. Therefore, we suspect that it may be related to DDS1.

To test if issues are really related to DDS1, we kept DDS1 on but used signal generator to provide modulation and demodulation.

Signal in use: 1dBm sent to EOM, 7dBm sent to mixer. The other in-loop components were the same. Then optimized phase and locked SHG loop and measured error signal spectrum. Figure 1 shows this spectrum and we can see that 20kHz noise is still present.

Other checks could be done:

0. try to do the same test with this entry but DDS needs to be off

1. try to use different rack to power up DDS/servo

2. try to see if 20kHz appear in GRMC error signal

3. try to see if 20kHz signal appears in signal beofre demodulation

4. try to change modulation/demodulation frequency a bit

5. try to use SR560 pre-amplifier to lock SHG

Marc, Michael, Yuhang

We found the peaks in OPO and SHG spectrums were quite similar. To make sure they could have the same source, we made measurement of their coherence. Figure 1 shows their coherence.

Marc, Michael, Yuhang

By take the spectrum of IRMC reflection (IRMC unlocked), we checked the main laser intensity noise. Figure one shows this result.

We could see that it is quite flat. So it should not cause problems for SHG/OPO error signals.

Marc, Michael, Yuhang

We checked the spectrum of power supply of rack. This rack contains PLL servos.

The check was done for -24V/ground and 24V/ground. However, there were issues happened at some point. The issue is that I connected -24V to ground by mistake once. Then I heard the sound from the rack. I switched off the rack power supply as soon as I heard the sound. After that happed, I took another two spectrums. Figure 1 shows these spectrums.

Marc and Yuhang (Eleonora remotely)

As reported in elog2322, we had oscillation in SHG length control error signal. Those peaks appear around about 20kHz and show harmonics.

The attached figure shows SHG transmission spectrum, which shows the same peaks found in error signal spectrum. But those peaks were not present in SHG transmission old measurement (elog1276).

We need to investigate more about this issue. One check could be measuring sound spectrum. Since these peaks also appear in OPO error signal spectrum, another check could be measuring the main laser amplitude noise.

Marc and Yuhang

For DDS1, we found the signals used for SHG/IRMC/OPO demodulation are smaller than 7dBm. However, the mixers require at least 7dBm signals. Therefore, we decide to install amplifiers for corresponding DDS channels. After the installation, the situation of DDS1 is shown as follows:

DDS1 CH0: DDS output = -8dBm output (for SHG/IRMC modulation)

DDS1 CH1: DDS output+18dB amplifier+power splitter = 7dBm output *2 (for SHG/IRMC demodulation)

DDS1 CH2: DDS output =  -8dBm output (for OPO modulation)

DDS1 CH3: DDS output+18dB amplifier= 10dBm output  (for OPO demodulation)

Since we are using internal amplifiers for SHG/IRMC/OPO demodulation, their old amplifiers will not be used.

We did the test and found that DDS1 board works well and they are outputing good values. Then we optimized all PDH signals, measured TFs and error signals. The results of measurements are attached.

Marc and Yuhang

The first test of DDS3 board showed problem about USB connection. Therefore, we checked the connection and soldering of USB. We found a soldering problem related to USB connector. After that, we tried to solder it again. Following problems about soldering cost us quite a lot of time:

1. The wires going through the breadboard holes are not straight, which make wires very diffcult to be removed

2. A relatively large hole needs to be soldered in order to fix USB on the breadboard. When the solder is applied to an inappropriate side of this large hole, it causes the USB outer shell touching ground. We checked a working DDS board, whose USB's outer shell is not connected to ground. Due to this inappropriate solder, we wasted a USB connector.

3. When fixing USB on the breadboard, we need to choose the two sides of the breadboard. But only one side will make a correct connection.

After solving these problems, we tested DDS3 board output signal magnitude and put attenuator to get required level of signals.

DDS3 CH0: DDS output+18dB amplifier+12dB attenuator = -2dBm output (for PLL CC)

DDS3 CH1: DDS output+18dB amplifier+12dB attenuator = -2dBm output (for PLL ppol)

DDS3 CH2: DDS output+18dB amplifier+power splitter = 7dBm output *2  (for CC1 and CCFC)

DDS3 CH3: DDS output+18dB amplifier+10dB attenuator = 0dBm output  (for CC2)

We compared the PLL phase noise for the cases of using -8dBm LO and -2dBm LO. From the datasheet of ADF4002, it requires LO from -5dBm to 2dBm. Therefore, we should prefer -2dBm LO. Figure 1 and 2 show the comparison of PLL phase noise. However, the shape of phase noise curve is not in agree with the measurement done in elog863, which needs further investigation.

On the other hand, higher LO also makes a higher phase noise. This is out of our expectation.

Michael, Marc and Yuhang

DDS signals usually give an output of -6dBm, which is not enough for many mixers. Due to the lack of enough LO power, we had issues, such as CCFC error demodulation. To solve this problem, Matteo ordered several amplifiers. The idea is to put them inside the DDS board and connect the DDS output directly to them.

Yesterday, Aso-san kindly provided us an instruction before the implementation of these amplifiers. Today, we followed the design of Matteo and implemented part of those amplifiers (for DDS2 and DDS3).

Figure 1 shows the connection done for an amplifier (We did five in total for today).

Figure 2 shows the DDS2 board before putting amplifier (we found unfiltered CH1 output is giving signal).

Figure 3 shows the DDS2 board after putting the amplifier.

Then I took it to TAMA and did several tests. In the beginning, I found the signal was not present in CH1. Then I changed CH1 from unfiltered CH1 to filtered CH1(shown in attached figure 4). After this, I discovered that signal (shown in figure 5) increase from -8dBm to 9dBm after amplifier implementation. This signal is used as LO to demodulate the filter cavity length error signal for GR. Figures 6 and 7 show the check of PDH amplitude for these two cases. The PDH becomes a bit smaller with a larger LO. I compared TF and GR locking length noise with these two cases.

Figure 8 shows TFs. After implementing the amplifier, the unity gain frequency is smaller while the phase margin is better. The amplified case also shows a better phase for higher (compared with UGF) frequency region.

Figure 9 shows error signals. After implementing the amplifier, the integrated length noise becomes less. This error signal is not calibrated. Besides, it maybe better to compare them again when they have almost the same unity gain frequency.

All amplifiers are also installed inside DDS3. We will test it tomorrow.

The time (around JST 2am 21st Dec 2020) of this sudden change has coincidence with an earthquake.

Marc and Yuhang

We found difficulty to align FC on this Monday. Then we checked oplev signals and found a sudden position change for END mirror (figure 1, we didn't find sudden change on INPUT).

By changing DC offset for END, its oplev sensing signals were recovered (figure 2).

Marc, Michael and Yuhang

In september, we had problem of FDS measurement, which is the FDS feature (rotation from sqz(asqz) to asqz(sqz)) disappeared when we locked CCFC loop. After that, it has been long time we didn't measure FDS again. Recently, we would like to change the FDS configuration. So we decide to redo the FDS measurement before going on. The important degradation sources are as following:

Green power: 25mW (11dB generated squeezing)

optical losses: 68%

CC2 loop introduced a 30dB attenuator for error signal (We found CC2 loop always had oscillation & CC2 loop could be only closed when the gain is small)

other parameters are kept the same with setting in this Feb. Besides, detuning was chosen to be 114Hz (this number is calculated from entry 2296)

The measurement was sometimes not stable today. This instability was the squeezing level going up and down for each measurement. However, this happened while CC1 and CC2 loop were both locked(a bit strange for me, we could check those spectrums). Anyway, we found some stable moments and took measurement.

According to the mentioned degradation sources, I tried to fit data and got results in attached figure 1. The detuning was fit to a larger detuning compared with setting. Besides, the fit curves don't match well with data. However, the good point is that FDS could be measured again with CCFC loop closed. 

As mixers need to be operated in saturation mode, I temporarily take the amplifier channel used for IRMC demodulation to amplify the signal from DDS. DDS provides about -6dBm signals. With the mentioned amplifier, LO was amplified to about 5dBm. At the same time, the RF signal was about -15dBm.

When we scan the CCFC phase with a sine wave, the demodulated signals will deviate from sine wave if the demodulation process has problems. So I did this test with 5dBm LO (shown in attached figure 1) for different RF power (-15dBm, -9dBm, -6dBm and -3dBm). These tests are in attached figures 2 to 5. All these figures seem to provide good shape demodulated signals (sinusoidal). From these figures, we could also see that the pk-pk signal also increases with the increase of RF power almost linearly (115mV, 206mV, 288mV, 380mV).

I also checked the CCFC error signals for these cases(figure 6,7,8). They are consistent with the error signals we found in elog2308. And apparently, better SNR is achieved with -3dBm RF power.

(We could add 12dB+12dB+3dB attenuator for the -3dBm signal to simulate a factor of ~25 decreases of CCSB power)