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YuhangZhao - 23:15, Monday 26 November 2018 (1119)Get code to link to this report
Recovery of PLL lock

Participaint: Aritomi, Eleonora, Chienming, Shurong and Yuhang

1. We checked the spectrum analyzers by signal generator. We found out

HP E4411B (the new one): Has a wrong amplitude value but higher bandwidth up to 1.5GHz.

HP 8563E(the old one which was used by Marco): Has a correct amplitude but the bandwidth is limited to 170MHz.

So we decide to check firstly by the new one and then tune beatnote frequency smaller than 170MHz. FIncally check amplitude by the old one.

2. The lesson we got from PLL locking

We need to load Marco set-up and remember to write this set-up into chip. How to change this set-up and implement it for the second board still needs to be investigated.

We checked the correction of PLL, we found now it is only positive. So we can bring initial frequency locked only when it is lower than reference frequency.

To do list:

1. investigate the amplification factor of each channel.

2. investigate the locking peformance of PLL(the highest locking frequency).

3. lock PLL to make both p-pol and s-pol resonant.

4. investigate how to apply lock for PLL board two.