Summary

When we were working with Yuhang in April, we noticed that the CC loop was very glitchy. I attempted to measure the CC PLL phase noise but got no signal.

Details

I attempted to measure PLL phase noise using the same method I did previously. To recap:

• The PLL outputs a sine wave
• If this is mixed with some local oscillator at the same frequency, then the output of the mixing will just be zero signal + phase noise
• The procedure is to put [name] PLL MON into RF and a local oscillator directly from the DDS3 into LO (last time I used 7.6 dBm).
• DDS3 outputs: Ch0 - CC LO 21 MHz, Ch1 - CC2, Ch2 - CC1, Ch3 - PPol LO 35 MHz - note that Ch1 and Ch3 are reversed compared to wiki/theses.
• Offsetting the PLL by 100 Hz should give a signal visible on the oscilloscope at about 0.08 V

I could see that the LO was generated from the DDS board (Ch3 - 50 MHz, 9 dBm), and that the CC PLL could lock. However, no signal came out of the mixer - the spectrum analyser just showed the same as when unplugged, and putting the signal into the oscilloscope gave nothing when the RF and LO were offset by 100 Hz.

Next time I will check the mixer and cables