According to elog2514, the current CC detuning should be ~72Hz and we have to change it by 18Hz to have the optimal detuning. Using the formula in elog1727, the CC PLL frequency should be changed by 2*18/1.91 = 18.85Hz. Since the current CC PLL frequency is 6.99701252 MHz, the optimal CC PLL frequency should be either 6.99703137 MHz or 6.99698367 MHz. By checking the CCFC error signal, I confirmed that 6.99703137 MHz is the correct one (In DDS, 6.99703139 MHz was set).
Here is the new CC PLL setting. I saved the DDS setting as "20210520_dds3_CCFC_check" for characterization of CCFC error signal and "20210520_dds3_CCFC_FDS" for CCFC FDS measurement.
| channel | function | frequency (MHz) | binary number |
| CH0 | CC PLL | 20.99109418 | 1010 10111111 01011000 00111110 |
| CH2 | CC1/CCFC demod | 13.99406279 | 111 00101010 00111010 11010100 |
| CH3 | CC2 demod | 6.99703139 | 11 10010101 00011101 01101010 |
Fig 1,2 show the measured CCFC error signal and locking accuracy, respectively. The CCFC calibration amplitude is 182mVpp. Now the CC detuning is 60Hz.
