R&D (FilterCavity)
YuhangZhao - 00:47, Thursday 21 February 2019 (1229)
Change locking scheme of coherent control PLL

From the datasheet of ADF4002 (page 3), there is REFIN input frequency limit from 20MHz to 300MHz. However, we used to send a 7MHz reference signal into REFIN. So in this case, it seems the old locking scheme of coherent control PLL can be improved.

So we decide to use 21MHz REFIN and divide it by 3. This 3 is the value of R.

Today we tried this new locking scheme. However, it still didn't work.

What we observed was PLL locked on the beat note while it goes away easily(Can we put an integrator?). By turning on slow, it can go back to locking point. But there is always overshot(still high gain?).

However, sometimes, we can lock it successfully. So it seems the shape of the locking filters should be improved. Now it works like a not optimized control loop. Maybe we should measure the open loop transfer function of it?