We tried to make s PLL working for 7MHz. At the same time, make p and s co-resonant. Then shift 7MHz of p. This is the procedure to lock PLL.

However, we found a good setting for that procedure brought us mode-hooping of p.

In the end, we found the temperature of OPO was changed accidentally from 7.05 to 7.9. After we brought back the temperature, we can lock PLL for coherent control without mode-hooping.

Next step is to check coherent control error signal. However, the reflection power drop for resonance is still not visible up to now.